So, I'm specing out a new MPI cluster here at work, and in doing so discovered that P4 Xeons are truly abominable. The highest-end version available uses a shared 533MHz (4 * 133MHz) front side bus, compared to an 800MHz bus on all recent P4 systems. That equates to 266MHz of bus bandwidth per processor when each processor is using the bus at saturation (which tends to happen when you have a CPU bound mesoscale atmospheric modelling program working with large data sets)
So, I fail to understand, why has Intel managed to make such monumental strides on the desktop P4 side (which now support dual channel DDR400 memory controllers) yet allowed Xeons to slip by the wayside?
Honestly, I see them completely losing their tenuous grasp on the low end server space to AMD in the near future.
So, I fail to understand, why has Intel managed to make such monumental strides on the desktop P4 side (which now support dual channel DDR400 memory controllers) yet allowed Xeons to slip by the wayside?
Honestly, I see them completely losing their tenuous grasp on the low end server space to AMD in the near future.
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